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Berkeley breathes
new life into silicon
Nanotransistors could hold Moore's Law at bay for decades
By David Pescovitz
The future of computing is headed toward a brick wall. Eventually,
the silicon industry's rule of thumb known as Moore's Law -- which
predicts that the number of transistors that can be packed on
a silicon integrated circuit doubles every 18 months -- will be
vetoed by the laws of physics and economics.
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| Wafers
such as these that Tsu-Jae King, left, and doctoral student
Yang-Kyu Choi are inspecting, have just come out of the "stepper,"
(out of view) the lab’s new state-of-the-art lithography
equipment used to print fine features on the surface of the
wafer. Once imprinted, the wafers are inspected and loaded
up for etching. "Yang-Kyu has made some of the world’s
smallest transistors," King points out. "Now we
want to prove they can work in the circuit. What we want is
circuit performance." Peg
Skorpinksi photo |
First proposed in 1965 by Gordon Moore, a Berkeley chemistry
alum who went on to co-found Intel, Moore's Law has proven itself
with a steady increase in computing power at proportionate decreases
in cost. At a certain scale though, today's transistors -- the
tiny on/off switches that make up integrated circuits -- will
become too unreliable and, perhaps even sooner, too expensive
to be practical. The private sector expects that day to come within
a decade or so. But a trio of Berkeley researchers designing the
world's smallest next-generation transistors aren't quite ready
to put Moore's Law to rest.
"We think we can keep shrinking the transistor for another
20 years," says Chenming
Hu of the Department of Electrical Engineering and Computer
Sciences who, with faculty colleagues Jeff
Bokor and Tsu-Jae
King and a team of graduate students, created new devices
that enhance performance while also enabling chips to keep shrinking.
"Even if the brick wall faced by Moore's Law can't be toppled,
it certainly could be pushed further out," says Hu.
To extend the life of Moore's Law in the long-term, and improve
computing power in the short-term, the Berkeley researchers are
proposing two new paradigms in silicon transistor design: FinFET
(Fin Field Effect Transistor) and UTB (Ultra-Thin Body). Ten times
smaller than today's transistors, the FinFET and UTB devices measure
less than 100 atoms across. Their Lilliputian scale means that
a trillion transistors could be packed on a chip that today holds
a mere one billion. That increase in processing power could lead
to ultra-fast and hyper-realistic medical simulations, handheld
foreign language translators that work in real time, and computers
that respond to natural spoken language.
While these applications are at least a dozen years away, the
FinFET and UTB research is already bearing fruit. Most recently,
the Berkeley researchers presented their progress in performance
and manufacturing processes at the 2001 International Electron
Devices Meeting (IEDM) in December. But Hu, Bokor, and King's
crew were not the only ones trumpeting advances in transistor
technology born, or at least furthered, at Cal. For starters,
an IBM research group, led by a former student of Bokor's, presented
their own positive FinFET findings.
"IBM was already working on this technology when they got
one of our Berkeley experts to go there," Bokor says of his
former student. "He sort of supercharged their project, and
we're all very proud of that."
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| Hu, Bokor, and King
(pictured counter-clockwise from top) inspect wafers, which
are fabricated in the MicroLab, then measured here, in the
Device Characterization Lab in Cory Hall. Peg Skorpinksi
photo |
Also at IEDM, Intel Corporation touted their newly announced
TeraHertz transistor, essentially a structural double of Berkeley's
UTB transistor. The company expects to add elements of the TeraHertz
technology into its product line as early as 2005.
"These various companies have our former students, so they
have the benefit of knowing the issues with laying out and designing
these circuits," King says. "I would think they have
a good chance at being very successful."
The FinFET and UTB project was born in 1996 out of a Defense Advanced
Research Projects Agency (DARPA) call for researchers to fabricate
a transistor that was 25 nanometers in length. (A nanometer is
one-billionth of a meter.) At the time, the smallest transistors
were 250 nanometers in length. A cloud of uncertainty hovered
over the silicon industry as researchers expressed concern that
the future of silicon transistors, especially past the 50-nanometer
size, was grim.
"The expectation then was that DARPA's size requirement could
only be met by exotic approaches like quantum devices that are
not compatible with circuits for real applications," Hu says.
"But we submitted a proposal to do it with silicon, which
is Berkeley's specialty. We believed in the future of silicon
when most people were doubting it."
In 1999, the Berkeley team dropped their 18-nanometer transistor
design in DARPA's lap, christened as FinFET. In 2000, DARPA honored
the group's success with the prestigious Award for Technical Achievement.
Currently, the project is funded under Microelectronics Advanced
Research Corporation and Semiconductor Research Corporation grants.
To understand how Berkeley broke the world record in silicon
scaling, a bit of transistor terminology is necessary. Complementary
metal-oxide semiconductor (CMOS) is the technology commonly used
to fabricate transistors. Semiconductors are exactly what the
name implies. The crystalline materials, including silicon and
germanium, aren't as good as, say, copper wire in allowing electrons
to flow through. But they're not that bad at it either. Also,
impurities such as boron can be added to the semiconductor to
selectively enhance its conductivity. This process, called "doping,"
results in a semiconductor with either an abundance of mobile
positive charge (a "p-type" material) or an abundance
of mobile negative charge (an "n-type" material).
The transistor itself contains three terminals: the source, the
gate, and the drain. In the most common transistor type, the source
and the drain, doped n-type, reside in a p-type body. The conductivity
of the p-type region between the source and drain is controlled
by the gate, which is located directly above the channel with
a thin interposing oxide layer. This layer is needed to prevent
electrical current from flowing between the gate and the channel.
The size of a transistor actually refers to the length of the
gate, which corresponds to the spacing between the source and
the drain. Applying a positive voltage to the gate attracts the
negatively charged electrons from the source into a surface channel,
creating a continuous n-type layer for current to flow between
the source and drain. At this point, the transistor is "on."
If the voltage at the gate is removed, the n-type channel layer
cannot be maintained, switching the transistor "off."
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