Cooler Chip Designs
by David Pescovitz
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Professor
Borivoje Nikolic holds several of his low-power integrated
circuits. (David Pescovitz photo)
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Every eighteen months or so, new integrated circuits with more
transistors packed into the same amount of space continue to
step up the already-dazzling graphics of our desktop PCs and
the capabilities of the portable devices in our pockets. In
the background though, chip designers are faced with a potential
showstopper: the challenge of power consumption and heat dissipation.
The faster the chip, the higher its power requirements and
power density. Intel CTO Patrick Gelsinger has said that if
the problem is not solved, chips available by the end of the
decade will, proportionately for their size, generate the heat
of a nuclear reactor.
To cool things off, UC Berkeley professor Borivoje Nikolic of the
Department of Electrical Engineering and Computer Sciences, is
developing techniques to dramatically reduce power consumption,
without sacrificing much performance. The optimization challenges
are two sides of the same coin.
"All of the tools that the industry relies on were built to
extract the maximum performance from transistors," Nikolic
says. "But
we now want to get the maximum performance for a given power or
the minimum power for required performance."
The solution, Nikolic explains, is "energy-performance optimization" at
every level of chip design, from the overall architecture of the
integrated circuit down to the tiniest components of the transistors.
While the optimization techniques differ depending on the level,
the aim is the same: balance the trade-offs between energy and
performance.
To help chip designers find this sweet spot, Nikolic and his graduate
students, are continuing UC Berkeley's rich history of developing
groundbreaking tools for integrated circuit design. The new software
tool analyzes new chip designs to pinpoint the trade-offs between
energy and performance.
"To reduce power consumption, you must first understand where
your power goes," Nikolic says.
So far, the tool has shown that saving energy to reduce performance
in one aspect of a chip design does not mean that the chip's overall
performance will dramatically suffer. Instead, redesigning another
part of the chip could make-up for the performance loss at a much
lower energy cost.
"With a performance reduction of just a few percent, we might
be able to cut a chip's power consumption in half," Nikolic
says.
To demonstrate their novel approach, the researchers are examining
several chip power-intensive chip components in light of the power
constraint issue. The first is to identify the most ideal design
for an adder, the digital logic circuits used by a computer to
add two or more binary numbers. In collaboration with IBM, the
researchers are also designing a new low-power Floating Point Unit
(FPU), the part of a microprocessor that handles complex calculations
involving decimal points. Many high-end graphics applications,
for example, depend on powerful FPUs.
"Ninety-nine
percent of designs for the most basic components don't make sense
when you think about power constraints," Nikolic
says.
While low-power integrated circuits are necessary to keep next
generation chips from sizzling, they're also essential for the
continued proliferation of mobile computing technology.
"The key is to minimize the energy requirements to extend the
battery life," Nikolic says. "So we ask, what is
the lowest amount of energy needed for a certain computational
task?" To
that end, Nikolic is collaborating with Robert Broderson, a
professor in EECS and the co-director of the Berkeley Wireless
Research Center (BWRC), and others on low-power integrated
circuits
for telecommunications applications like mobile phones and
wireless handheld computers. One novel approach was proposed
by Yun Chiu,
a graduate student working with Nikolic and EECS professor
Paul Gray. (Gray is also the University's Executive Vice Chancellor
and Provost). Chiu's method involves substituting a high-accuracy,
high-power analog-to-digital converter component with one that
uses less power but is also prone to error. Then, a robust
digital
signal processor that doesn't suck down much juice can correct
the errors.
Ultimately, the aim of all Nikolic's research is to prevent
the performance curve of future chips from burning itself out
with
power problems.
Borivoje Nikolic's home page
Berkeley Wireless Research Center
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Updated 01/01/04.
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