The Death
and Rebirth of Silicon
by David Pescovitz
Professors
Hu, Bokor, and King inspect wafers, whch are fabricated
in the MicroLab, then measured here, in the Device Characterization
Lab in Cory Hall. (Click for larger
image.)
Peg Skorpinski photo
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The future of
computing is headed toward a brick wall. Within a decade or so,
the silicon industry's rule of thumb known as Moore's Law —
which predicts that the number of transistors that will be packed
on a silicon integrated circuit doubles every 18 months — be
vetoed by the laws of physics and economics. Or will it?
"We think we can keep shrinking the transistor for another
20 years," says Chenming Hu of the Department of Electrical
Engineering and Computer Sciences who, with faculty colleagues Jeff
Bokor, Tsu-Jae King, Vivek Subramanian, and a team of graduate students,
created new transistors that enhance performance while also enabling
chips to keep shrinking. "Even if the brick wall faced by Moore's
Law can't be toppled, it certainly could be pushed further out,"
says Hu.
To extend the life of Moore's Law in the long-term, and improve
computing power in the short-term, the Berkeley researchers are
proposing two new paradigms in silicon transistor design: FinFET
(Fin Field Effect Transistor) and UTB (Ultra-Thin Body). Ten times
smaller than today's transistors, the FinFET and UTB devices measure
less than 100 atoms across. Their Lilliputian scale means that a
trillion transistors could be packed on a chip that today holds
a mere one billion. That increase in processing power could lead
to ultra-fast and hyper-realistic medical simulations, handheld
foreign language translators that work in real time, and computers
that respond to natural spoken language.
To understand how Berkeley broke the world record in silicon scaling,
a bit of transistor terminology is necessary. Complementary metal-oxide
semiconductor (CMOS) is the technology commonly used to fabricate
transistors. Semiconductors are exactly what the name implies —
the material conducts electricity with varying levels of success.
Also, impurities such as boron can be added to the semiconductor
to selectively enhance its conductivity. This process, called "doping,"
results in a semiconductor with either an abundance of mobile positive
charge (a "p-type" material) or an abundance of mobile
negative charge (an "n-type" material).
Probe
stations, such as this one in the Device Characterization
Lab, measure devices as small as a single transistor. (Click
for larger image.)
Peg Skorpinski photo
|
The transistor
itself contains three terminals: the source, the gate, and the drain.
In the most common transistor type, the source and the drain, doped
n-type material, resides in a p-type body. The conductivity of the
p-type region between the source and drain is controlled by the
gate, which is located directly above the channel with a thin interposing
oxide layer. This layer is needed to prevent electrical current
from flowing between the gate and the channel. The size of a transistor
actually refers to the length of the gate, which corresponds to
the spacing between the source and the drain. Applying a positive
voltage to the gate attracts the negatively charged electrons from
the source into a surface channel, creating a continuous n-type
layer for current to flow between the source and drain. At this
point, the transistor is "on." If the voltage at the gate
is removed, the n-type channel layer cannot be maintained, switching
the transistor "off."
The problem is that as the gate length is shrunk and the source
and drain are pushed so close together (less than 100 atoms apart),
more electrons can sneak through during the "off" state.
Professor
Tsu-Jae King looks at a wafer, whose fine features will
be etched with some of the world's smallest transistors.
(Click for larger image.)
Peg Skorpinski photo
|
In the FinFET
design, a thin vertical silicon "fin" is built between
the source and drain. Then the gate electrode material is deposited
on both sides of the fin resulting in a double gate structure, one
on each side of the channel.
"It's
like trying to stop a bleeding vein," Hu says. "You could
press down on the vein, but it would be much more effective if you
could get another finger behind the vein and pinch it closed."
Hu, Bokor, and King's second transistor design, the Ultra-Thin Body
device, employs a very different engineering innovation to shorten
gate lengths while preventing leakage. In today's transistors, most
of the leakage occurs deep in the body of the transistor below the
gate. The UTB approach is to eliminate that material except for
the top-most portion of the channel that is well-controlled by the
gate.
"To continue the bleeding analogy, the UTB approach is like
closing off a vein by pushing it against a hard surface like a bone,"
Hu says.
With the end of silicon in sight, the Berkeley research into FinFET
and UTB structures is cranking along with an emphasis on honing
the production process for mass manufacture. Once the advantages
are on the table and the manufacturing kinks ironed out, it's up
to the private sector to take the ball and run with it.
"The brick wall facing today's transistors is still a ways
off," Hu says. "The industry can continue for a while.
But at what point would a company become more competitive to convert
to our new structure? Our challenge is to make that switch more
compelling."
Chenming Hu
Tsu-Jae King
Jeffrey Bokor
Vivek Subramanian
Lab Notes is published online by the Public Affairs Office of the UC Berkeley College of Engineering. The Lab Notes mission is to illuminate groundbreaking
research underway today at the College of Engineering that will dramatically change our lives tomorrow.
Editor, Director of Public Affairs: Teresa Moore
Writer, Researcher: David Pescovitz
Designer: Robyn Altman
Subscribe or send comments to the Engineering Public Affairs Office: lab-notes@coe.berkeley.edu.
© 2002 UC Regents.
Updated 6/20/02.
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